The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIGS. 1A and 1B, a successive-approximation-register analog-to-digital converter (SAR ADC) 100 is shown. In FIG. 1A, the SAR ADC 100 includes a sample-and-hold circuit (S/H) 102, SAR logic 104, a digital-to-analog (DAC) converter 106, and a comparator 108. The S/H circuit 102 receives an analog input signal to be converted and outputs an input voltage VIN to the comparator 108.
The SAR logic 104 includes an N-bit register to implement a binary search algorithm to convert the analog input signal. The N-bit register is initially set to a midscale value, for example, to 100 . . . 00, where the most significant bit (MSB) is set to 1. The SAR logic 104 outputs the midscale value stored in the N-bit register to the DAC 106. The DAC 106 converts the N-bit input received from the SAR logic 104 and outputs a voltage VDAC to the comparator 108. Since the N-bit input is 100 . . . 00, VDAC=VREF/2, where VREF is the reference voltage provided to the SAR ADC 100.
The comparator 108 compares VIN to VDAC and determines if VIN is less than VDAC or greater than VDAC. If VIN is greater than VDAC, the output of the comparator 108 is a logic high, or 1, and the MSB of the N-bit register remains at 1. Conversely, if VIN is less than VDAC, the output of the comparator 108 is a logic low, or 0, and the MSB of the register is cleared to logic 0. This step is generally referred to as MSB testing.
The SAR logic 104 then moves to the next bit and forces that bit high. The comparator 108 performs another comparison. The process continues to the least significant bit (LSB), which concludes the conversion process. When the conversion is complete, an N-bit digital word is output from the N-bit register. The N-bit word is a digital representation of the analog input. This process of converting an analog signal using the SAR logic 104, the DAC 106, and the comparator 108 is called the binary search algorithm.
In FIG. 1B, an example of a 4-bit conversion using the binary search algorithm is shown (i.e., N=4). In the example, the DAC 106 initially receives 10002 from a 4-bit register in the SAR logic 104. That is, bit 3, the MSB, of the 4-bit register is set to 1. A first comparison shows, for example, that VIN<VDAC. Therefore, bit 3 of the 4-bit register is reset to 0. The DAC 106 then receives 01002, and a second comparison is performed. If VIN>VDAC, for example, bit 2 of the 4-bit register remains at 1. The DAC 106 then receives 01102, and a third comparison is performed. Bit 1 is reset to 0 if VIN<VDAC, for example, and the DAC 106 then receives 01012 for a final comparison. Finally, bit 0 remains at 1 if, for example, VIN>VDAC. Thus, a 4-bit word 0101 is output from the 4-bit register, which is a digital representation of the analog input.
The S/H circuit 102 shown in FIG. 1A can be embedded in the DAC 106. Many SAR ADCs use a capacitive DAC that provides an inherent S/H function. A capacitive DAC includes an array of N capacitors with binary-weighted values and one dummy LSB capacitor.
Referring now to FIG. 2, an example of a 16-bit capacitive DAC 200 connected to a comparator 202 is shown. The DAC 200 includes an array of capacitors having binary weighted values. One end of each capacitor is connected to a common terminal. The other end of each capacitor is connected to a switch. The switch connected to each capacitor, except the dummy capacitor, connects the capacitor to an analog input signal (VIN), a reference voltage (VREF), or ground (GND) depending on control signals received from the SAR logic 104 shown in FIG. 1. The switch connected to the dummy capacitor connects the dummy capacitor to VIN or ground. A switch selectively connects the common terminal to ground. The common terminal is connected to a first input of the comparator 202. A second input of the comparator 202 is connected to ground.
During an acquisition phase, the common terminal of the capacitors is connected to ground, and the other terminals of the capacitors are connected to the analog input signal (VIN). After acquisition, the common terminal is disconnected from ground, and the other terminals of the capacitors are disconnected from VIN. Effectively, a charge proportional to the input voltage is trapped on the capacitors. The other terminals of the capacitors are then connected to ground, driving the common terminal negative to a voltage equal to −VIN.
As a first step in the binary search algorithm, a bottom plate of the MSB capacitor is disconnected from ground and connected to VREF. This drives the common terminal in the positive direction by an amount equal to ½VREF. Therefore, VCOMMON=−VIN+½×VREF. The output of the comparator 202 is logic 1 if VCOMMON<0 (i.e., VIN>½×VREF). The output of the comparator 202 is logic 0 if VIN<½×VREF. If the comparator output is logic 1, then the bottom plate of the MSB capacitor stays connected to VREF. Otherwise the bottom plate of the MSB capacitor is connected back to ground. The bottom plate of the next smaller capacitor is then connected to VREF, and a new VCOMMON voltage is compared to ground. This process continues until all the bits have been determined. In general, VCOMMON=−VIN+(BN-1×VREF/2)+(BN-2×VREF/4)+(BN-1×VREF/8)+ . . . +(B0×VREF/2N-1 (B_comparator output/ADC output bits)).